1. Field of the Invention
The present invention relates to an integrated injection logic (I.sup.2 L) type semiconductor device and a method of producing the same. The I.sup.2 L type semiconductor memory device in accordance with the present invention is used for a bipolar static random access memory (RAM) device, a logic circuit or the like.
2. Description of the Prior Art
Prior art memory cells of the I.sup.2 L type memory devices are illustrated in FIGS. 1, 2, 3 and 4. FIGS. 1 and 2 illustrate an npn coupled type memory cell, while FIGS. 3 and 4 illustrate a pnp coupled type memory cell. FIGS. 1 and 3 illustrate the structure of the memory cells, while FIGS. 2 and 4 illustrate the circuit diagrams of the memory cells.
In FIG. 1, a p.sup.+ type injector region J, a contact portion J.sub.W of said p.sup.+ type injector region, p.sup.+ type base regions B, contact portions B.sub.0 and B.sub.1 of said p.sup.+ type base regions, n.sup.+ type collector regions C(n.sup.+), contact portions C.sub.h0, C.sub.h1, C.sub.s0 and C.sub.s1 of said n.sup.+ type collector regions, writing-in or reading-out lines D.sub.0 and D.sub.1, and a word line W are illustrated. An opposite word line W- connected to the semiconductor body is not shown in FIG. 1. As illustrated in FIGS. 1 and 2, the PNP type transistors Q.sub.2 and Q.sub.3 are constituted by lateral bipolar transistors, each of which transistors comprises a, p type injector region J as an emitter, an n type region N.sub.B as a base and p type region B as collectors. The NPN type transistors Q.sub.0 and Q.sub.1 are constituted by vertical bipolar transistors, each of which transistors comprises an n type region C(n.sup.+) as a collector, a p type base region B as a base and an n type region N.sub.B, which is located under the base region B, as an emitter. Thus, both the PNP type transistors Q.sub.2 and Q.sub.3 and the NPN type transistors Q.sub.0 and Q.sub.1 have the n type region N.sub.B as a common connecting body.
In FIG. 3, a p.sup.+ type injector region J, a contact portion J.sub.w of said p.sup.+ type injector region, p.sup.+ type base regions B, contact portions B.sub.0 and B.sub.1 of said p.sup.+ type base regions B, n.sup.+ type collector regions C(n.sup.+), contact portions C.sub.h0 and C.sub.h1 of said n.sup.+ type collector regions, contact portions C'.sub.so and C'.sub.s1 of emitter regions E(p.sup.+) of a lateral pnp transistor for detection, writing-in or reading-out lines D.sub.0 and D.sub.1, and a word line W are illustrated. An opposite word line W.sup.- is connected to the semiconductor body and is not shown in FIG. 3. As illustrated in FIGS. 3 and 4, the PNP type illustrated. As illustrated in FIGS. 3 and 4, the PNP type transistors Q.sub.2 and Q.sub.3 are constituted by lateral bipolar transistors, each of which transistors comprises a p type injector region J as a common emitter, an n region N.sub.B as a common base and p type regions B as collectors. The NPN type transistors Q.sub.0 and Q.sub.1 are constituted by vertical bipolar transistors, each of which transistors comprises an n type region C(n.sup.+) as a collector, a p type base region B as a base and the n type region N.sub.B, which is located under the base region B, as an emitter. The PNP type transistors Q.sub.4 and Q.sub.5 are constituted by lateral bipolar transistors, each of which transistors comprises a p type region B as a collector, an n type region N.sub.BD connected to the n type region B as a base and a p.sup.+ type region E(P.sup.+) as an emitter. Thus, all of the PNP type transistors Q.sub.2 and Q.sub.3, NPN type transistors Q.sub.0 and Q.sub.1 and the PNP type transistors Q.sub.4 and Q.sub.5 have the n type regions N.sub.B and N.sub.BD as a common connecting body.
In FIGS. 1, 2, 3 and 4, B.sub.0, C.sub.h0, C.sub.s0 and D.sub.0 are related to the "0" (or "1") side transistor Q.sub.0, while B.sub.1, C.sub.h1, C.sub.s1 and D.sub.1 are related to the "1" (or "0") side transistor Q.sub.1.
In the memory cell of FIGS. 1 and 3, since the structures of the transistors Q.sub.0 and Q.sub.1 of the flip-flop circuit are symmetrical, the operations of the transistors Q.sub.0 and Q.sub.1 of the flip-flop circuit are symmetrical. Accordingly the currents which energize the transistors Q.sub.0 and Q.sub.1 are caused to be precisely symmetrical, and no asymmetry in the operations of the writing-in and the reading-out of information occurs. Also, since the currents delivered from the injector region J are uniform in every direction, high injection efficiency is obtained and, accordingly, excellent operating characteristics of the flip-flop circuit are obtained.
However, in the manufacture of the memory cell of FIGS. 1 and 3 it is necessary to use a masking pattern which defines an opening in the insulation layer over the p.sup.+ type injector region through which an electrical connection between the p.sup.+ type injector an the conductor is formed. In order to avoid misalignment of the mask, it is necessary to make the size of the device large. Also, conductors for internal connections of the device occupy a predetermined volume of space in the device.
Therefore, in the prior art, it was difficult to reduce the size of an I.sup.2 L type memory device.
The prior art I.sup.2 L memory cell is described in, for example, "Injection-coupled Memory: A High-Density Static Bipolar Memory" by S. K. Wiedmann, IEEE Journal of Solid-state Circuits, Vol. SC-8, No. 5, October 1973, and in the Japanese patent application No. 51-71855 entitled "A Semiconductor Memory Device".